This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-259108, filed Aug. 29, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention pertains to a semiconductor integrated circuit that operates a power voltage by an increased voltage. More particularly, the present invention relates to a semiconductor integrated circuit adopted to improve hot carrier durability of an element to which such increased voltage is applied.
2. Description of the Related Art
Recently, in a DRAM (Dynamic Random Access Memory) that is a kind of semiconductor integrated circuit, a high-level signal in a word line is raised to a voltage higher than a power voltage, thereby achieving high speed data readout and write operations. The high-level signal of the word line signal is set to an increased voltage that is higher than the power voltage, whereby a high voltage is applied to a gate of a selection transistor that is connected to the word line during memory cell selection. In this manner, the conductive resistance of this selection transistor is lowered, and a greater readout or write current flows in the selection transistor as compared with a case in which the power voltage is applied to the gate of the selection transistor, whereby high speed data readout and write operations are achieved.
However, by using the increased voltage that is higher than the power voltage, there increases a substrate current that flows in a semiconductor substrate on which the DRAM is formed. In this manner, an increase in hot carrier is produced, and there occurs transistor degradation such as an increased threshold voltage of the transistor or a decrease in conductance.
In order to reduce such transistor degradation due to an increase in hot carrier and extend service life, there has been conventionally adopted a technique for connecting another transistor in series with a transistor to which the increased voltage is applied. The degradation of service life of the transistor due to a hot carrier is closely associated with a substrate current. That is, it is known that, if the substrate current is reduced by one digit, the service life increases by about three digits. The substrate current is represented by an exponential function of a voltage xe2x80x98Vdsxe2x80x99 between a source and a drain. Therefore, in order to extend the service life of a transistor, it is most effective to alleviate the voltage conditions and reduce electrical field intensity applied to the transistor. A plurality of transistors are connected in series, whereby a voltage is divided by a plurality of these transistors, and a voltage applied to one transistor is reduced.
In general, an N-channel transistor is weaker than a P-channel transistor relevant to a hot carrier. Because of this, it is effective to connect transistors in series only to the N-channel side in a CMOS configured DRAM at which both of the P-channel and N-channel transistors are provided.
FIG. 1 shows an example of a conventional row decoder circuit in the CMOS configured DRAM, the circuit being provided as an example-of a semiconductor integrated circuit for which the above described hot carrier countermeasure is taken. In general, in a row decoder circuit, a plurality of decode circuits are arranged in an array manner in order to drive a plurality of word lines WL. Here, only one decode circuit for driving one word line WL is shown.
This row decoder circuit is composed of: a partial decode circuit 50 for decoding an address signal of a plurality of bits; two pre-driver circuits 51 and 52 cascade-connected so as to sequentially invert an output of this partial decode circuit 50; a latch circuit 53 for latching an output of the partial decode circuit 50 and a word line driver circuit 54 for driving the word line WL based on an output of the pre-driver circuit 52 at a final stage.
The partial decode circuit 50 is of a pre-charge/discharge type, and is composed of a P-channel transistor P11 and three N-channel transistors N11 to N13. This partial decode circuit 50 outputs a decode signal based on a plurality of bits, i.e., address signals AX, AY, and AZ of three bits in this example, after a pre-charge period based on the pre-charge signal PREC has completed.
These two pre-driver circuits 51 and 52 are each composed of discrete P-channel transistors P12 and P13, respectively, and two pairs of N-channel transistors N14 and N15 and N-channel transistors N16 and N17, respectively. These circuits sequentially invert and supply outputs of the partial decode circuit 50.
The word line driver circuit 54 is composed of one P-channel transistor P14 and two N-channel transistors N18 and N19. This circuit drives the word line WL upon receipt of an output of the pre-driver circuit 52.
The latch circuit 53 is composed of one P-channel transistor P15 and two N-channel transistors N20 and N21. This latch circuit 53 latches a decode signal according to an original input address signal even after the input address signal level is changed after the pre-charge period in the partial decode circuit 50 has completed, and further, a decode output signal based on the input address signal has been determined. The latch circuit 53 is operatively controlled based on a pre-charge signal PREC and an output of the pre-driver circuit 51.
Here, in order to set the high-level side voltage of a word line drive signal to an increased voltage that is higher than the power voltage, an increased voltage VPP to which a power voltage VCC is increased is applied to each source of each of the respective P-channel transistors in the pre-driver circuits 51 and 52, the latch circuit 53, and the word line driver circuit 54.
In such a configured row decoder circuit, an increased voltage VPP is supplied as a power voltage of each of the pre-driver circuits 51 and 52 and the word line driver circuit 54. Further, in order to reduce the electric field intensity applied to each of the N-channel side of the pre-driver circuits 51 and 52 and the word line driver circuit 54, N-channel transistors N14, N16, and N18, each of which causes the increased voltage VPP to be applied to each gate, are connected in series, respectively, to N-channel transistors N15, N17, and N19.
In this way, the N-channel transistors N14, N16, and N18, each of which causes the increased voltage VPP to be applied to each gate, are connected in series, respectively, to the N-channel transistors N15, N17, and N19, whereby the maximum value of the voltage applied to the source of each of the N-channel transistors N15, N17, and N19 becomes VPP-VthN (where VthN denotes a threshold value of an N-channel transistor), and a voltage xe2x80x98Vdsxe2x80x99 applied between the drain and source of each of the N-channel transistors N15, N17, and N19 is reduced by VthN as compared with the maximum value VPP of the voltage applied to the word line WL, as shown in FIG. 2. In this manner, transistor degradation such as an increased threshold voltage or a decreased conductance based on an increase in substrate current as described previously is restrained.
However, in the word line driver circuit 54, the transistor N18 is connected in series to the N-channel transistor N19. Because of this, if an attempt is made to take a current drive force at the N-channel side so as to be equal to a case in which the transistor N18 is not connected, a total size of the transistors at the N-channel side increases to four times its original size.
If the size of the N-channel side transistor that configures the word line driver circuit 54 increases, a vicious cycle is entered in which the pre-driver circuits 52 and 51, used to drive the enlarged transistor, must also be enlarged, thus increasing the overall transistor size.
For example, when the N-channel side of the word line driver circuit 54 is composed of only one transistor, the channel width of such a transistor is defined as W, and the N-channel side is composed of two transistors connected in series, if an attempt is made to obtain a current drive force equal to a case in which only one transistor is provided, it is required to set the channel width of the two transistors connected in series to 2W, respectively. That is, when hot carrier countermeasures are taken, the total element size of the N-channel side transistors is four times as large as the original size in the word line driver circuit 54.
Typically, the element size of the N-channel side transistor of the pre-driver circuit 52 for driving the word line driver circuit 54 is required to be W/3 where the element size in the word line driver circuit 54 is defined as W, assuming that the circuit is driven by a fan-out 3. Thus, the element size of the N-channel side transistor of the pre-driver circuit 51 for driving this pre-driver circuit 52 is required to be W/9. Further, if the channel width of each of the N-channel transistors in the word line driver circuit 54 is defined as 2W, the channel widths at the two N-channel sides, each of which configures the pre-driver circuit 52, are required to be 2W/3, respectively, and the channel widths at the two N-channel side, each of which configures the pre-driver 51, are required to be 2W/9, respectively.
As a result, the total of the channel widths of the N-channel side transistors in the pre-driver circuits 51 and 52 and the word line driver circuit 54 is {2W+(2W/3)+(2W/9)}xc3x972=52W/9≈5.78 W.
In this way, in the conventional row decoder circuit for which hot carrier countermeasures are taken, the circuit layout increases in size as compared with a case in which hot carrier countermeasures are not taken.
In particular, if the hot carrier countermeasures as described above are taken for a row decoder circuit for driving a word line, the length of the decoder circuit is a factor that defines the chip size of the DRAM itself, thus causing a substantial increase in chip size.
In addition, an increase in circuit layout size denotes that power consumption increases accordingly.
If hot carrier countermeasures are taken for conventional semiconductor integrated circuits using such increased high voltages, there occurs a problem that power consumption increases and the chip size is increased.
The present invention has been made in order to solve the foregoing problem. It is an object of the present invention to provide a semiconductor integrated circuit using an increased voltage, wherein an increase in chip size is reduced, and hot carrier countermeasures can be taken without causing a significant increase in power consumption.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
a first node to which a first voltage is applied;
a plurality of first transistors of a first channel each having a current path which has one end and the other end and a gate, the one end of the current path being connected to the first node;
a plurality of second nodes to which the other end of the current paths of the plurality of first transistors is connected, respectively;
a plurality of second transistors of a second channel each having a current path which has one end and the other end and a gate, the one end of each of the current path is connected to the second node, respectively;
a third node to which the other ends of the current paths of the plurality of the second transistors are connected in common;
a fourth node to which a second voltage lower than the first voltage is applied; and
a third transistor of the second channel having a current path and a gate, wherein the current path is connected between the third node and the fourth node, and a third voltage higher than the second voltage is applied to the gate.
According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
a first node to which a first voltage obtained by increasing a power voltage is applied;
a plurality of decode circuits arranged in an array manner, the plurality of decode circuits each comprising:
a partial decode circuit for decoding an address signal;
pre-driver circuits each having at least one inverter circuit which comprises a first transistor of a P-channel having a source a drain, and a gate, the source being connected to the first node, and a second transistor of an N-channel having a source, a drain and a gate, the drain being connected to a drain of the first transistor, an output of the partial decode circuit being inputted to the gate of each of the first and second transistors; and
a word line driver circuit comprises: a third transistor of a P-channel having a source, a drain and a gate, the source being connected to the first node; and a fourth transistor of an N-channel having a source, a drain, and a gate, the drain being connected to a drain of the third transistor, and the source being connected to a source of the second transistor, an output of the pre-driver circuit being supplied to drive a word line;
a second node to which a second voltage lower than the first voltage is applied; and
a fifth transistor of an N-channel having a source, a drain, and a gate, a source-drain path is connected between a source common connection node of the second and fourth transistors and the second node, and a third voltage higher than the second voltage is applied to the gate.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.